1. Field of the Invention
The present invention relates to fabricating integrated circuit devices and, more particularly, to the formation of metallization layers exhibiting reduced signal processing time.
2. Description of the Related Art
In the field of semiconductor production, there is a tendency to reduce the dimensions of semiconductor devices in an integrated circuit. At the same time, the clock frequency of a digital circuit, such as a CPU, is routinely increased from one design generation to a subsequent design generation.
As the clock frequency rises, however, the electrical characteristics of the various metallization layers within the integrated circuit steadily gain in importance. High resistivities of the contacts and wiring lines connecting the semiconductor devices, as well as high capacitances resulting from those contacts and lines, increase the fall and rise times of the electrical signals that are transmitted in the integrated circuit, thereby impairing device performance.
In this respect, it is also important to consider the stray capacitances of adjacent contacts and wiring lines. Increased capacitance between adjacent conductors is undesirable because it may delay signal propagation along the conductors, and it may result in increased power consumption by the integrated circuit device, as this capacitance must be charged-up during each operating cycle. As the capacitance of two conductors is inversely proportional to the distance between the conductors, reducing the device dimensions inevitably leads to an increase of the stray capacitance of adjacent conductors. Moreover, in very large scale integration (VLSI) circuits in which multiple metallization layers are formed, the vertical distance between adjacent layers can not be arbitrarily enlarged to reduce the capacitance between these layers, since a maximum vertical distance is determined by the aspect ratio of the via holes connecting two adjacent metallization layers. Exact control of the dimensions of the via holes, however, is necessary to obtain narrowly spaced apart vias for reduced circuit dimensions as well as for a sufficient thickness of the vias to guarantee a low electrical resistivity of the via.
The present invention is directed to a method for solving, or at least reducing the effects of, some or all of the aforementioned problems.
The present invention is directed to a semiconductor device having reduced signal processing time and a method of making same. In one illustrative embodiment of the present invention, the device is comprised of a layer of porous material having a density ranging from approximately 20-80% of the density from which the porous material is made, and a plurality of conductive interconnections formed in the layer of material.
One illustrative embodiment of the present invention comprises providing a layer of material having an original density, reducing the density of the layer of material to approximately 20-80% of the original density of the starting material, forming at least one opening in the layer with a reduced density, and forming a conductive interconnection in the opening.